This page tries to show to pros and the cons of several architectures.
- Architecture 1: SFP+ connected to an ethernet PHY (e.g. VSC8491) chip on the SBC
- Architecture 2: SFP+ connected to the Zynq on the SDR board
- Architecture 3 (2bis) : SFP+ connected to the Zynq on the SDR board with additional RJ45 on the SBC connected to a PHY chip
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Architecture 1 (quick result) |
Architecture 2 (future proof) |
Architecture 3 (2bis) (quick result and future proof) |
Hardware design |
- CON: we need clock chip on the SBC
- PRO : very simple SDR, we could even replace the Zynq by a simple FPGA
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- CON: need more connections between SBC and SDR (SFP+ from SBC to SDR, 1 PCIe lane from SDR to SBC)
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- CON: we need clock chip on the SBC
- CON: need more connections between SBC and SDR (SFP+ from SBC to SDR, 1 PCIe lane from SDR to SBC)
- CON: need more connectors and more components
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Firmware (Zynq) design |
- PRO: very simple design (almost exactly the same as SDR100)
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- CON: need to finish the Zynq firmware before having ethernet connection on the CPU
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- PRO: we can use the ethernet phy from SBC and very simple FPGA firmware until the full Zynq firmware is developed
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Features |
- CON: doesn't support CPRI or RDMA
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- PRO: we can support CPRI/eCPRI/ethernet/RDMA
- PRO: we could do an autonomous RRH without SBC (as long as you have SFP+ connector board able to connect to the SDR)
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